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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD780053,780054,780055,780056,780058
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The PD780053,780054,780055,780056 and 780058 are members of the PD780058 subseries in the 78K/0 series. These microcontrollers suppress the EMI (Electro Magnetic Interference) noise internally generated to the lower level than the existing PD78054 subseries. In addition, they have many peripheral hardware units such as an 8-bit resolution A/D converter, 8-bit resolution D/A converter, timers, serial interface, real-time output ports, and interrupt functions. A flash memory model that can operate on the same voltage as the mask ROM models, PD78F0058, and various development tools are now under development. The funcitons are explaned in detail in the following User's Manuals. Be sure to read these manuals when designing your system.
PD780058, 780058Y Subseries User's Manual : U12013E
78K/0 Series User's Manual - Instruction : U12326E
FEATURES * Internal high-capacity ROM & RAM
Item Part Number
Program Memory (ROM) Internal high-speed RAM
Data Memory
Internal buffer RAM Internal expanded RAM
PD780053 PD780054 PD780055 PD780056 PD780058
24K bytes 32K bytes 40K bytes 48K bytes 60K bytes
1024 bytes
32 bytes
None
1024 bytes
* * * * * * * *
External memory expansion space: 64K bytes Minimum instruction execution time changeable from high speed (0.4 s) to ultra low-speed (122 s) I/O ports: 68 pins (N-ch open-drain : 4 pins) 8-bit resolution A/D converter : 8 channels (VDD = 2.7 to 5.5 V) 8-bit resolution D/A converter : 2 channels (VDD = 2.7 to 5.5 V) Serial interface Timer Operating voltage range : 3 channels : 5 channels : VDD = 1.8 to 5.5 V
APPLICATION FIELDS
Car audio systems, cellular phones, pagers, printers, AV systems, cameras, PPCs, and vending machines
The information in this document is subject to change without notice. Document No. U12182EJ1V1DS00 (1st edition) Date Published January 1999 N CP(K) Printed in Japan The mark shows major revised points.
(c)
1997
PD780053, 780054, 780055, 780056, 780058
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
PD780053GC-xxx-8BT PD780053GK-xxx-BE9 PD780054GC-xxx-8BT PD780054GK-xxx-BE9 PD780055GC-xxx-8BT PD780055GK-xxx-BE9 PD780056GC-xxx-8BT PD780056GK-xxx-BE9 PD780058GC-xxx-8BT PD780058GK-xxx-BE9
Remark
xxx indicates ROM code suffix.
2
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
78K/0 SERIES PRODUCT DEVELOPMENT
The following shows the 78K/0 Series products development. Subseries name are shown inside frames.
Products in mass production Products under development Y subseries products are compatible with I2C bus. EMI-noise reduced version of the PD78078
Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083
Inverter control
PD78078Y PD78070AY PD780018YNote PD780058YNote PD78058FY PD78054Y PD780034Y PD780024Y PD78018FY PD78014Y PD78002Y
A timer was added to the PD78054 and external interface was enhanced ROM-less version of the PD78078 Serial I/O of the PD78078Y was enhanched and the function is limited Serial I/O of the PD78054 was enhanced and EMI-noise was reduced EMI-noise reduced version of the PD78054 UART and D/A converter were added to the PD78014 and I/O was enchanced A/D converter of the PD780024 was enchanced Serial I/O of the PD78018F was added EMI-noise reduced version of PD78018F Low-voltage (1.8 V) operation version of the PD78014, with larger selection of ROM and RAM capacities An A/D converter and 16-bit timer were added to the PD78002 An A/D converter was added to the PD78002 Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V)
64-pin
PD780988
FIPTM drive
On-chip inverter control circuit and UART. EMI-noise was reduced.
78K/0 Series
100-pin 100-pin 80-pin 80-pin
PD780208 PD780228 PD78044H PD78044F
LCD drive
I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53 I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48 N-ch open drain was added to the PD78044F, Display output total: 34 Basic subseries for driving FIP, Display output total: 34
100-pin 100-pin 100-pin
PD780308 PD78064B PD78064
PD780308Y PD78064Y
The SIO of the PD78064 was enhanced and ROM, RAM capacity increased EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, On-chip UART
IEBusTM supported 80-pin 80-pin
PD78098B PD78098
EMI-noise reduced version of the PD78098 An IEBus controller was added to the PD78054
Meter control 80-pin
PD780973
On-chip controller/driver for automotive meter drive
Note Under planning
Preliminary Data Sheet
3
PD780053, 780054, 780055, 780056, 780058
The following lists the main functional differences between subseries products.
Function Subseries Name Control ROM Capacity 32 K - 40K 48 K - 60K - 24 K - 60 K 2ch 3ch (time division UART: 1ch) 3ch (UART: 1ch) 61 68 2.7 V 1.8 V Timer 8-bit 16-bit Watch WDT 4ch 1ch 1ch 1ch 8-bit 10-bit A/D A/D 8ch - 8-bit D/A 2ch Serial Interface 3ch (UART : 1ch) VDD MIN. External Value Expansion 1.8 V
I/O 88
PD78075B PD78078 PD78070A PD780058 PD78058F PD78054 PD780034 PD780024 PD78014H PD78018F PD78014 PD780001 PD78002 PD78083
48 K - 60 K 16 K - 60 K 8 K - 32 K - 8ch 8ch - -
69
2.7 V 2.0 V
3ch (UART: 1ch, time division 3-wire: 1ch) 2ch
51
1.8 V
53
8 K - 60 K 8 K - 32 K 8K 8 K - 16 K - - 1ch - 32 K - 60 K 3ch Note - 1ch - 8ch - 8ch - 1ch (UART: 1ch) 3ch (UART: 2ch) 1ch 39 53 33 47 1.8 V 4.0 V - 2.7 V -
Inverter control FIP drive
PD780988
PD780208 PD780228 PD78044H PD78044F
32 K - 60 K 48 K - 60 K 32 K - 48 K 16 K - 40 K 48 K - 60 K
2ch 3ch 2ch
1ch - 1ch
1ch - 1ch
1ch
8ch
-
-
2ch 1ch
74 72 68
2.7 V 4.5 V 2.7 V
-
2ch 2ch 1ch 1ch 1ch 8ch - - 3ch (time division UART: 1ch) 2ch (UART : 1 ch) 57 2.0 V -
LCD drive
PD780308 PD78064B PD78064
32 K 16 K - 32 K 40 K - 60 K 32 K - 60 K 32 K 6ch - - 1ch 8ch - - 2ch 1ch 1ch 1ch 8ch - 2ch
IEBus supported LV
PD78098B PD78098 PD78P0914
3ch (UART : 1 ch)
69
2.7 V
2ch
54
4.5 V
Note 16-bit timer : 2 channels 10-bit timer : 1 channel
4
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
OVERVIEW OF FUNCTION
Product Name Item Internal memory ROM High-speed RAM Buffer RAM Expanded RAM
PD780053
24K bytes
PD780054
32K bytes
PD780055
40K bytes 1024 bytes 32 bytes
PD780056
48K bytes
PD780058
60K bytes
Memory space General registers Minimum instruction execution
None 64 K bytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip minimum instruction execution time cycle modification function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (at 5.0 MHz operation) 122 s (at 32.768 kHz operation) * * * * 16-bit operation Multiplication/division (8 bits x 8 bits,16 bits / 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD correction, etc. : 68 :2 : 62 :4
1024 bytes
time
When main system clock selected When subsystem clock selected
Instruction set
I/O ports
Total * CMOS input * CMOS I/O * N-ch open-drain I/O * * * *
A/D converter D/A converter Serial interface
8-bit resolution x 8 channels (VDD = 2.7 to 5.5 V) 8-bit resolution x 2 channels (VDD = 2.7 to 5.5 V) 3-wire serial I/O/SBI/2-wire serial I/O mode selectable: 1 channel 3-wire serial I/O mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel * 3-wire/serial I/O/UART mode (on-chip time division transfer function) selectable: 1 channel * * * * 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer : : : : 1 2 1 1 channel channels channel channel
Timer
Timer output Clock output
3 (14-bit PWM output x 1) 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (at main system clock: 5.0 MHz operation) 32.768 kHz (at subsystem clock: 32.768 kHz operation) 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: 5.0 MHz operation) Maskable Non-maskable Software Internal interrupt : 13, external interrupt : 6 Internal interrupt : 1 1 Internal : 1, external : 1 VDD = 1.8 to 5.5 V TA = -40 to +85C * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
Buzzer output Vectored interrupt sources
Test input Supply voltage Operating ambient temperature Package
Preliminary Data Sheet
5
PD780053, 780054, 780055, 780056, 780058
CONTENTS
1. 2. 3.
PIN CONFIGURATION (TOP VIEW) .............................................................................................. BLOCK DIAGRAM .........................................................................................................................
7 9
PIN FUNCTIONS ............................................................................................................................ 10
3.1 3.2 3.3 PORT PINS .............................................................................................................................................. 10 OTHER PINS ............................................................................................................................................ 12 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ................................. 14
4. 5.
MEMORY SPACE ............................................................................................................................ 18 PERIPHERAL HARDWARE FUNCTION FEATURES .................................................................. 19
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 PORTS ...................................................................................................................................................... 19 CLOCK GENERATOR ............................................................................................................................. 20 TIMER/EVENT COUNTER ...................................................................................................................... 20 CLOCK OUTPUT CONTROL CIRCUIT ................................................................................................. 23 BUZZER OUTPUT CONTROL CIRCUIT ................................................................................................ 23 A/D CONVERTER .................................................................................................................................... 24 D/A CONVERTER .................................................................................................................................... 25 SERIAL INTERFACES ............................................................................................................................ 25 REAL-TIME OUTPUT PORT FUNCTIONS ............................................................................................ 27
6.
INTERRUPT FUNCTIONS .............................................................................................................. 28
6.1 6.2 INTERRUPT FUNCTIONS ....................................................................................................................... 28 TEST FUNCTIONS .................................................................................................................................. 32
7. 8. 9.
EXTERNAL DEVICE EXPANSION FUNCTIONS .......................................................................... 33 STANDBY FUNCTION .................................................................................................................... 33 RESET FUNCTION .......................................................................................................................... 33
10. INSTRUCTION SET ......................................................................................................................... 34 11. ELECTRICAL SPECIFICATIONS ................................................................................................... 36 12. PACKAGE DRAWINGS .................................................................................................................. 63 APPENDIX A. DEVELOPMENT TOOLS ........................................................................................... 65 APPENDIX B. RELATED DOCUMENTS ........................................................................................... 68
6
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
1. PIN CONFIGURATION (TOP VIEW)
* 80-pin plastic QFP (14 x 14 mm)
PD780053GC-xxx-8BT, 780054GC-xxx-8BT, 780055GC-xxx-8BT, 780056GC-xxx-8BT, 780058GC-xxx-8BT
* 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
PD780053GK-xxx-BE9, 780054GK-xxx-BE9, 780055GK-xxx-BE9, 780056GK-xxx-BE9, 780058GK-xxx-BE9
P01/INTP1/TI01
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RxD0 P71/SO2/TxD0 P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB/TxD1 P24/BUSY/RxD1 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P40/AD0 P41/AD1
1 2 3 4 5 6 7 8 9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
P00/INTP0/TI00
P05/INTP5
P04/INTP4
P03/INTP3
P02/INTP2
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
XT1/P07
AVREF0
VDD0
VDD1
VSS0
XT2
X1
X2
IC
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
10 11 12 13 14 15 16 17 18 19
41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VSS1
P56/A14
P57/A15
P60
P61
P62
P63
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P52/A10
P53/A11
P54/A12
Cautions 1. 2.
Directly connect the IC (Internally Connected) pins to VSS0 or VSS1. Connect the AVSS pin to VSS0.
Remarks 1. xxx indicates ROM code suffix. 2. If the microcontroller is used in an application where the noise generated from the microcontroller must be suppressed, it is recommended that power be supplied to VDD0 and VDD1 from separate sources, and that VSS0 and VSS1 be connected to separate group lines, to improve noise immunity.
Preliminary Data Sheet
P55/A13
P64/RD
P50/A8
P51/A9
7
PD780053, 780054, 780055, 780056, 780058
A8-A15 AD0-AD7 ANI0-ANI7 ANO0, ANO1 ASCK ASTB AVREF0, 1 AVSS BUSY BUZ IC INTP0-INTP5 P00-P05, P07 P10-P17 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P70-P72 P120-P127 : Address Bus : Address/Data Bus : Analog Input : Analog Output : Asychronous Serial Clock : Address Strobe : Analog Reference Voltage : Analog Ground : Busy : Buzzer Clock : Internally Connected : Interrupt from Peripherals : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 : Port7 : Port12 P130, P131 PCL RD RESET RTP0-RTP7 RxD0, RxD1 SB0, SB1 SCK0-SCK2 SI0-SI2 SO0-SO2 STB TI00, TI01 TI1, TI2 TO0-TO2 TxD0, TxD1 VDD0, VDD1 VSS0, VSS1 WAIT WR X1, X2 XT1, XT2 : Port13 : Programmable Clock : Read Strobe : Reset : Real-Time Output Port : Receive Data : Serial Bus : Serial Clock : Serial Input : Serial Output : Strobe : Timer Input : Timer Input : Timer Output : Transmit Data : Power Supply : Ground : Wait : Write Strobe : Crystal (Main System Clock) : Crystal (Subsystem Clock)
8
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
2. BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 TO2/P32 TI2/P34 P00 P01-P05 P07 P10-P17
16-bit TIMER/ EVENT COUNTER
PORT0
8-bit TIMER/ EVENT COUNTER 1 8-bit TIMER/ EVENT COUNTER 2
PORT1
PORT2
P20-P27
PORT3 WATCHDOG TIMER
P30-P37
WATCH TIMER
PORT4
P40-P47
SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SI1/P20 SO1/P21 SCK1/P22 STB/TxD1/P23 BUSY/RxD1/P24 BUSY/RxD1/P24 STB/TxD1/P23 SI2/RxD0/P70 SO2/TxD0/P71 SCK2/ASCK/P72 ANI0/P10ANI7/P17 AVSS AVREF0
SERIAL INTERFACE 0 78K/0 CPU CORE SERIAL INTERFACE 1 ROM
PORT5
P50-P57
PORT6
P60-P67
PORT7
P70-P72
PORT12 SERIAL INTERFACE 2 RAM PORT13
P120-P127
P130,P131
A/D CONVERTER
REAL-TIME OUTPUT PORT
RTP0/P120RTP7/P127
ANO0/P130, ANO1/P131 AVSS AVREF1 INTP0/P00INTP5/P05
D/A CONVERTER
EXTERNAL ACCESS
INTERRUPT CONTROL
AD0/P40AD7/P47 A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67
BUZ/P36
BUZZER OUTPUT SYSTEM CONTROL VDD0, VDD1 VSS0, VSS1 IC
PCL/P35
CLOCK OUTPUT CONTROL
RESET X1 X2 XT1/P07 XT2
Remark The internal ROM and RAM capacities differ depending on the product.
Preliminary Data Sheet
9
PD780053, 780054, 780055, 780056, 780058
3. PIN FUNCTIONS 3.1 PORT PINS (1/2)
Pin Name P00 P01 P02 P03 P04 P05 P07Note 1 P10-P17 Input Input/ output Input only Port 1 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by softwareNote 2. Port 2 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input Input I/O Input Input/ output Port 0 7-bit input/output port Function Input only Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. After Reset Input Input DualFunction Pin INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 XT1 ANI0-ANI7
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40-P47
Input/ output
Input
SI1 SO1 SCK1 STB/TxD1 BUSY/RxD1 SI0/SB0 SO0/SB1 SCK0
Input/ output
Port 3 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software.
Input
TO0 TO1 TO2 TI1 TI2 PCL BUZ --
Input/ output
Port 4 8-bit input/output port. Input/output can be specified in 8-bit unit. When used as an input port, on-chip pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection.
Input
AD0-AD7
Notes 1. When using the P07/XT1 pins as an input port, set 1 in the bit 6 (FRC) of the processor clock control register (PCC). On-chip feedback resistor of the subsystem clock oscillator should not be used. 2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input pins, set port 1 to input mode. Use of the on-chip pull-up resistor is cancelled automatically.
10
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
3.1 PORT PINS (2/2)
Pin Name P50-P57 I/O Input/ output Function Port 5 8-bit input/output port. LED can be driven directly. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 6 8-bit input/outport port. Input/output can be specified bit-wise. N-ch open-drain input/ output port. On-chip pullup resistor can be used by mask option. LED can be driven directly. When used as an input port, on-chip pull-up resistor can be used by software. Port 7 3-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 12 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Port 13 2-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. After Reset Input DualFunction Pin A8-A15
P60 P61 P62 P63 P64 P65 P66 P67 P70 P71 P72 P120-P127
Input/ output
Input
--
RD WR WAIT ASTB
Input/ output
Input
SI2/RxD0 SO2/TxD0 SCK2/ASCK
Input/ output
Input
RTP0-RTP7
P130, P131
Input/ output
Input
ANO0, ANO1
Preliminary Data Sheet
11
PD780053, 780054, 780055, 780056, 780058
3.2 OTHER PINS (1/2)
Pin Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 SI0 SI1 SI2 SO0 SO1 SO2 SB0 SB1 SCK0 SCK1 SCK2 STB BUSY RxD0 RxD1 TxD0 TxD1 ASCK TI00 TI01 TI1 TI2 TO0 TO1 TO2 PCL BUZ RTP0-RTP7 AD0-AD7 Output Output Output Input/ output Output Output Output Input Input Asynchronous serial interface serial clock input. External count clock input to the 16-bit timer (TM0) Capture trigger signal input to the capture register (CR00) External count clock input to the 8-bit timer (TM1) External count clock input to the 8-bit timer (TM2) 16-bit timer (TM0) output (dual-function as 14-bit PWM output) 8-bit timer (TM1) output 8-bit timer (TM2) output Clock output (for main system clock, subsystem clock trimming). Buzzer output. Real-time output port by which data is output in synchronization with a trigger. Low-order address/data bus at external memory expansion. Input Input Input Input Input Input Input Output Asynchronous serial interface serial data output. Input Output Input Input Serial interface automatic transmit/receive strobe output. Serial interface automatic transmit/receive busy input. Asynchronous serial interface serial data input. Input Input Input Input/ output Input/ output Serial interface serial data input/output. Input Output Serial interface serial data output. Input Input Serial interface serial data input. Input I/O Input Function External interrupt request input for which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. After Reset Input DualFunction Pin P00/TI00 P01/TI01 P02 P03 P04 P05 P25/SB0 P20 P70/RxD P26/SB1 P21 P71/TxD P25/SI0 P26/SO0 Serial interface serial clock input/ output Input P27 P22 P72/ASCK P23/TxD1 P24/RxD1 P70/SI2 P24/BUSY P71/SO2 P23/STB P72/SCK2 P00/INTP0 P01/INTP1 P33 P34 P30 P31 P32 P35 P36 P120-P127 P40-P47
A8-A15 RD WR
High-order address bus at external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Input
P50-P57 P64 P65
12
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
3.2 OTHER PINS (2/2)
Pin Name WAIT ASTB I/O Input Output Function Wait insertion at external memory access. Strobe output which latches the address information output at port 4 to access external memory. A/D converter analog input. D/A converter analog output. A/D converter reference voltage input (dual-function as analog power supply). D/A converter reference voltage input. A/D converter, D/A converter ground potential. Use at the same potential as VSS0. System reset input. Main system clock oscillation crystal connection. After Reset Input Input DualFunction Pin P66 P67 P10-P17 P130, P131 -- -- --
ANI-ANI7 ANO0, ANO1 AVREF0 AVREF1 AVSS
Input Output Input Input -- Input Input -- Input -- -- -- -- -- --
Input Input -- -- --
RESET X1 X2 XT1 XT2 VDD0 VSS0 VDD1 VSS1 IC
-- -- --
-- -- -- P07 -- -- -- -- -- --
Subsystem clock oscillation crystal connection.
Input --
Port block positive power supply. Port block ground potential. Positive power supply (except for port and analog blocks). Ground potiential (except for port and analog blocks). Internally connected. Connect to VSS0 or VSS1 directly.
-- -- -- -- --
Preliminary Data Sheet
13
PD780053, 780054, 780055, 780056, 780058
3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, see Figure 3-1. Table 3-1. Input/Output Circuit Type of Each Pin (1/2)
Input/Output Circuit Type 2 8-C
Pin Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P07/XT1 P10/ANI0-P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB/TxD1 P24/BUSY/RxD1 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0-P47/AD7 P50/A8-P57/A15 P60-P63 P64/RD P65/WR P66/WAIT P67/ASTB
I/O Input Input/output
Recommended Connection when Not Used Connect to VSS0. Independently connect to VSS0 through resistor.
16 11-D 8-C 5-H 8-C 5-H 8-C 10-B
Input Input/output
Connect to VDD0. Independently connect to VDD0 or VSS0 through resistor.
5-H
8-C
5-H
5-N 5-H 13-J 5-H
Independently connect to VDD0 through resistor. Independently connect to VDD0 or VSS0 through resistor. Independently connect to VDD0 through resistor. Independently connect to VDD0 or VSS0 through resistor.
14
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
Table 3-1. Input/Output Circuit Type of Each Pin (2/2)
Input/Output Circuit Type 8-C 5-H 8-C 5-H
Pin Name P70/SI2/RxD0 P71/SO2/TxD0 P72/SCK2/ASCK P120/RTP0P127/RTP7 P130/ANO0 , P131/ANO1 RESET XT2 AVREF0 AVREF1 AVSS IC
I/O Input/ output
Recommended Connection when Not Used Independently connect to VDD0 or VSS0 through resistor.
12-C
Independently connect to VSS0 through resistor.
2 16 --
Input -- Leave open. Connect to VSS0. Connect to VDD0. Connect to VSS0.
--
Connect to VSS0 or VSS1 directly.
Preliminary Data Sheet
15
PD780053, 780054, 780055, 780056, 780058
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 2 Type 8-C VDD0
pullup enable IN data VDD0 P-ch
P-ch
IN/OUT Schmitt-Triggered Input with Hysteresis Characteristic output disable N-ch VSS0
Type 5-H pullup enable VDD0 data
VDD0
Type 10-B
VDD0
P-ch
pullup enable VDD0 data IN/OUT P-ch
P-ch
P-ch
IN/OUT open drain output disable VSS0 N-ch
output disable
N-ch VSS0
input enable Type 5-N VDD0 Type 11-D pullup enable data V DD0 P-ch VDD0 P-ch IN/OUT IN/OUT output disable N-ch VSS0 output disable Comparator N-ch P-ch + VSS0
pullup enable VDD0 data P-ch
P-ch
N-ch VSS0 VREF (Threshold Voltage)
input enable
16
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
Figure 3-1. Pin Input/Output Circuits (2/2)
Type 12-C pullup enable VDD0 data P-ch IN/OUT output disable input enable N-ch VSS0 P-ch Analog Output Voltage N-ch Type 13-J VDD0 Mask Option IN/OUT data output disable VSS0 VDD0 N-ch VSS0 VDD0 Type 16 feed back cut-off P-ch
P-ch
XT1
XT2
RD
P-ch
Middle-High Voltage Input Buffer
Preliminary Data Sheet
17
PD780053, 780054, 780055, 780056, 780058
4. MEMORY SPACE
Figure 4-1 shows the PD780053/780054/780055/780056/780058 memory map. Figure 4-1. Memory Map
FFFFH Special Function Registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH
General Registers 32 x 8 bits
FA7FH Use Prohibited F800H F7FFH
Internal High-Speed RAM Note 3 FB00H FAFFH Use Prohibited Data Memory Space FAE0H FADFH FAC0H FABFH FA80H FA7FH
Internal Expanded RAM 1024 x 8 bits F400H F3FFH Use Prohibited Note 2 F000H nnnnH Program Area 1000H 0FFFH
Note 1
Internal Buffer RAM 32 x 8 bits
Use Prohibited 0800H 07FFH External Memory Program Memory Space nnnnH + 1 nnnnH 0080H 007FH
CALLF Entry Area
Program Area
CALLT Table Area 0040H 003FH Vector Table Area
Internal ROM
Note 3
0000H
0000H
Notes 1. PD780058 only 2. When the external device expansion function is used with the PD780058, set the internal ROM capacity to 56K bytes or less using the memory size switching register (IMS). 3. The internal ROM capacity depends on the products (see the next table).
Internal ROM Last Address nnnnH 5FFFH 7FFFH 9FFFH BFFFH EFFFH
Relevant Product Name
PD780053 PD780054 PD780055 PD780056 PD780058
18
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
5. PERIPHERAL HARDWARE FUNCTION FEATURES 5.1 PORTS
The following three types of I/O ports are available. * CMOS input (P00, P07) * CMOS input/output (P01-P05, port 1-port 5, P64-P67, port 7, port 12, port 13) * N-channel open-drain input/output (P60-P63) Total Table 5-1. Port Functions
Name Port 0 Pin Name P00, P07 P01-P05 Port 1 Port 2 Port 3 P10-P17 Dedicated input port pins Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. P20-P27 P30-P37 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Port 4 P40-P47 Input/output port pins. Input/output specifiable in 8-bit units. When used as input port pins, on-chip pull-up resistor can be used by software. Port 5 P50-P57 Test flag (KRIF) is set to 1 by falling edge detection. Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. LED direct drive capability. Port 6 P60-P63 N-channel open-drain input/output port pins. Input/output specifiable bit-wise. On-chip pull-up resistor can be used by mask option. LED direct drive capability. P64-P67 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Port 7 Port 12 P70-P72 P120-P127 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Port 13 P130, P131 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Function
: : : :
2 62 4 68
Preliminary Data Sheet
19
PD780053, 780054, 780055, 780056, 780058
5.2 CLOCK GENERATOR
Two types of generators, a main system clock generator and a subsystem clock generator, are avaibable. The minimum instruction execution time can also be changed. * 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s/12.8 s (main system clock: at 5.0 MHz operation) * 122 s (subsystem clock: at 32.768 kHz operation) Figure 5-1. Clock Generator Block Diagram
XT1/P07 XT2
Subsystem Clock Oscillator
fXT Watch Timer, Clock Output Function Prescaler 1
X1 X2
Main System fX Clock Oscillator Scaler STOP fX 2
2 Clock to Peripheral Hardware
Selector
fXX
Prescaler fXX fXX fXX 2 22 23 fXX fXT 24 2 Selector Standby Control Circuit
Wait Control Circuit
CPU Clock (fCPU)
To INTP0 Sampling Clock
5.3 TIMER/EVENT COUNTER
The following five channels of the timer/event counter are available. * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter * Watch timer * Watchdog timer : 2 channels : 1 channel : 1 channel Table 5-2. Operations of Timer/Event Counter
16-Bit Timer/ Event Counter Operation Interval timer External event counter Timer output PWM output Pulse width measurement Square wave output Ono-shot pulse output Interrupt request 1 channel 1 channel 1 output 1 output 1 input 1 output 1 output 2 8-Bit Timer/ Event Counter 2 channels 2 channels 2 outputs -- -- 2 outputs -- 2 Watch Timer 1 channel -- -- -- -- -- -- 2 Watchdog Timer 1 channel -- -- -- -- -- -- 1
mode
Function
20
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal Bus INTP1 TI01/P01/INTP1 Selector 16-Bit Capture/ Compare Register (CR00)
INTTM00
Match Watch Timer Output 2fXX fXX fXX/2 fXX/2 2 TI00/P00/INTP0 Edge Detector Match Selector 16-Bit Timer Register (TM0L) Clear
PWM pulse Output Control Circuit
Output Control Circuit
TO0/P30
Selector INTTM01 INTP0
16-Bit Capture/ Compare Register (CR01)
Internal Bus
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal Bus INTTM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector Match
Match fXX/2-fXX/29 fX/211 TI1/P33 Selector 8-Bit Timer Register 1 (TM1) Selector Clear 8-Bit Timer Register 2 (TM2) Clear Selector Selector
Output Control Circuit
TO2/P32 INTTM2
fXX/2-fXX/29 fX/211 TI2/P34
Output Control Circuit Internal Bus
TO1/P31
Preliminary Data Sheet
21
PD780053, 780054, 780055, 780056, 780058
Figure 5-4. Watch Timer Block Diagram
fW 2 14
Selector fXX/2 7 fXT
fW 24 fW 25 fW 26 fW 27 fW 28 fW 29
5-Bit Counter Selector
fW 2 13
Selector
fW
Prescaler
INTWT
Selector
INTTM3 To 16-Bit Timer/ Event Counter
Figure 5-5. Watchdog Timer Block Diagram
fXX 23
Prescaler
fXX 24
fXX 25
fXX 26
fXX 27
fXX 28
fXX 29
fXX 2 11
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request
22
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
5.4 CLOCK OUTPUT CONTROL CIRCUIT
The clock with the following frequency can be output as a clock output. * 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (main system clock: at 5.0 MHz operation) * 32.768 kHz (subsystem clock: at 32.768 kHz operation) Figure 5-6. Clock Output Control Circuit Configuration
fXX fXX/2 fXX/2 2 fXX/2 3 fXX /2 4 fXX /2 5 fXX /2 6 fXX /2 7 fXT Selector Synchronization Circuit Output Control Circuit PCL/P35
5.5 BUZZER OUTPUT CONTROL CIRCUIT
The clock with the following frequency can be output as a buzzer output. * 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (main system clock: at 5.0 MHz operation)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
f XX /2 9 f XX /2 10 f XX /2 11 Selector Output Control Circuit BUZ/P36
Preliminary Data Sheet
23
PD780053, 780054, 780055, 780056, 780058
5.6 A/D CONVERTER
An A/D converter of 8-bit resolution x 8 channels is incorporated. The following two types of the A/D conversion operation start-up methods are available. * Hardware start * Software start Figure 5-8. A/D Converter Block Diagram
Series Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 ANI6/P16 ANI7/P17 Succesive Approxmation Register (SAR) AVSS Selector AVSS Tap Selector Sample & Hold Circuit Voltage Comparator AVREF0 (dual-funciton as analog power supply)
INTP3/P03
Edge Detection Circuit
Control Circuit
INTAD INTP3
A/D Conversion Result Register (ADCR)
Internal Bus
24
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
5.7 D/A CONVERTER
A D/A converter of 8-bit resolution x 2 channels is available. Conversion method is R-2R resistor ladder method. Figure 5-9. D/A Converter Block Diagram
AVREF1
ANOn
Selector DACSn Write AVSS INTTMx
D/A Conversion Value Set Register n (DACSn)
DAMm D/A Converter Mode Register
Internal Bus
n m x
= 0, 1 = 4, 5 = 1, 2
5.8 SERIAL INTERFACES
Three channels of the clocked serial interface are incorporated. * Serifal interface channel 0 * Serifal interface channel 1 * Serifal interface channel 2 Table 5-3. Types and Functions of Serial Interface
Function 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmit/receive function SBI (serial bus interface) mode 2-wire serial I/O mode Asynchronous serial interface (UART) mode (on-chip time division transfer function) (MSB first) (MSB first) Serial Interface Channel 0 (MSB/LSB first switchable) Serial Interface Channel 1 (MSB/LSB first switchable) (MSB/LSB first switchable) Serial Interface Channel 2 (MSB/LSB first switchable)
--
--
-- -- -- --
-- --
(Dedicated baud rate generator incorporated)
Preliminary Data Sheet
25
PD780053, 780054, 780055, 780056, 780058
Figure 5-10. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25 Selector SO0/SB1/P26 Serial I/O Shift Register 0 (SIO0) Output Latch
Selector
Bus Release/Command/ Acknowledge Detection Circuit Serial Clock Counter
Busy/Acknowledge Output Circuit
SCK0/P27
Interrupt Request Signal Generator
INTCSI0
fXX/2-fXX/28 Serial Clock Control Circuit Selector TO2
Figure 5-11. Serial Interface Channel 1 Block Diagram
Internal Bus
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer RAM
Automatic Data Transmit/Receive Interval Specification Register (ADTI) Match
SI1/P20
Serial I/O Shift Register 1 (SIO1)
SO1/P21 5-Bit Counter STB/TxD1/P23 Handshake Control Circuit
BUSY/RxD1/P24
SCK1/P22
Serial Clock Counter
Interrupt Request Signal Generator
INTCSI1
fXX/2-fXX/2 Serial Clock Control Circuit Selector TO2
8
26
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
Figure 5-12. Serial Interface Channel 2 Block Diagram
Internal Bus
Receive Buffer Register (RXB/SIO2)
Direction Control Circuit
Direction Control Circuit
Transmit Shift Register (TXS/SIO2)
RxD0/SI2/P70 RxD1/BUSY/P24
Selector
Receive Shift Register (RXS)
Transmit Control Circuit
INTST
TxD0/SO2/P71 TxD1/STB/P23
Selector
Receive Control Circuit
INTSER INTSR/INTCSI2 SCK Output Control Circuit
ASCK/SCK2/P72
Baud Rate Generator
fXX-fXX/210
5.9 REAL-TIME OUTPUT PORT FUNCTIONS Data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently with timer interrupt request and external interrupt request generation in order to output to off-chip. This is real-time output function. And pins to output to off-chip are called real-time output ports. By using a real-time output port, a signal which has no jitter can be output. This is most applicable to control of stepping motor, etc. Figure 5-13. Real-Time Output Port Block Diagram
Internal Bus
INTP2 INTTM1 INTTM2
Output Trigger Control Circuit
Real-Time Output Real-Time Output Buffer Register Buffer Register High-order 4 Bits Low-order 4 Bits (RTBL) (RTBH) Real-Time Output Port Mode Register (RTPM)
Output Latch
P127
P120
Preliminary Data Sheet
27
PD780053, 780054, 780055, 780056, 780058
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6.1 INTERRUPT FUNCTIONS
There are interrupt functions, 21 sources of three different kinds, as shown below. * Non-maskable : * Maskable * Software : 1 1 : 19
Table 6-1. Interrupt Source List (1/2)
Note 1
Interrupt Type Non-maskable
Default Priority ---
Interrupt Source Name INTWDT Trigger Watchdog timer overflow (watchdog timer mode 1 selected) Watchdog timer overflow (interval timer mode selected) Pin input edge detection
Internal/ External Internal
Vector Table Address 0004H
Basic Configuration TypeNote 2 (A)
Maskable
0
INTWDT
(B)
1 2 3 4 5 6 7
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTCSI0
External
0006H 0008H 000AH 000CH 000EH 0010H
(C) (D)
End of serial interface channel 0 transfer End of serial interface channel 1 transfer Generation of serial interface channel 2 UART receive error
Internal
0014H
(B)
8
INTCSI1
0016H
9
INTSER
0018H
10
INTSR
End of serial interface channel 2 UART reception End of serial interface channel 2 3wire transfer End of serial interface channel 2 UART transmission
001AH
INTCSI2
11
INTS
001CH
Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 17, the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
28
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
Table 6-1. Interrupt Source List (2/2)
Interrupt Type
Note 1
Default Priority 12
Interrupt Source Name INTTM3 Trigger Reference time interval signal from watch timer Generation of match signal of 16-bit timer register and capture/compare register (CR00) Generation of match signal of 16-bit timer register and capture/compare register (CR01) Generation of match signal of 8-bit timer/event counter 1 Generation of match signal of 8-bit timer/ event counter 2 End of conversion by A/D converter BRK instruction execution
Internal/ External Internal
Vector Table Address 001EH
Basic Configuration TypeNote 2 (B)
13
INTTM00
0020H
14
INTTM01
0022H
15
INTTM1
0024H
16
INTTM2
0026H
17 Software --
INTAD BRK
0028H - 003EH (E)
Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 17, the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
Preliminary Data Sheet
29
PD780053, 780054, 780055, 780056, 780058
Figure 6-1. Interrupt Function Basic Configuration(1/2) (A) Internal non-maskable interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(B) Internal maskable interrupt
Internal Bus
MK
IE
PR
ISP
Interrupt Request
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Sampling Clock
Edge Detection Circuit
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
30
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
Figure 6-1. Interrupt Function Basic Configuration(2/2) (D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Edge Detection Circuit
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(E) Software interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
IF IE
: Interrupt request flag : Interrupt enable flag
ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag
Preliminary Data Sheet
31
PD780053, 780054, 780055, 780056, 780058
6.2 TEST FUNCTIONS
There are two sources of test functions as shown in Table 6-2. Table 6-2. Test Input Source List
Test Input Source Name INTWT INTPT4 Watch timer overflow Port 4 falling edge detection Trigger Internal/External Internal External
Figure 6-2. Test Function Basic Configuration
Internal Bus
MK
Test Input flag
IF
Standby Release Signal
IF
: Test input flag
MK : Test mask flag
32
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion functions connect external devices to areas other than the internal ROM, RAM and SFR. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
There are the following two standby functions to reduce the system power consumption. * HALT mode : The CPU operating clock is stopped. The average current consumption can be reduced by intermittent operation in combination with the normal operating mode. * STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock is stopped, so that the system operates with ultra-low power consumption using only the subsystem clock. Figure 8-1. Standby Function
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
CSS=1 CSS=0 HALT Instruction
Subsystem Clock Operation Note HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply to CPU is stopped, oscillation)
HALT Mode Note (Clock supply to CPU is stopped, oscillation)
Note The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set the MCC (bit 7 of the processor clock control register (PCC)) to stop the main system clock. The STOP instruction cannot be used. Caution When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. Remark CSS: Bit 4 of processor clock control regisrer (PCC).
9. RESET FUNCTION
There are the following two reset methods.
* External reset input by RESET pin * Internal reset by watchdog time runaway time detection
Preliminary Data Sheet
33
PD780053, 780054, 780055, 780056, 780058
10. INSTRUCTION SET
(1) 8-bit instruction MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand First Operand A #byte A
[HL + Byte]
r Note
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B] [HL + C]
$addr16
1
None
ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
ROR ROL RORC ROLC
r
MOV
MOV ADD ADDC SUB SUBC AND OR XOR CMP
INC DEC
B, C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV MOV MOV
DBNZ
DBNZ
INC DEC
PUSH POP
[DE] [HL] MOV ROR4 ROL4 [HL + Byte] [HL + B] [HL + C] X C MOV
MULU DIVUW
Note Except r = A
34
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
(2) 16-bit instruction MOV, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand First Operand AX #word ADDW SUBW CMPW MOVW MOVW MOVW MOVW MOVW Note MOVW MOVW MOVW MOVW AX rp Note MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW SP MOVW None
rp sfrp saddrp !addr16 SP
INCW, DECW PUSH, POP
Note Only when rp = BC, DE or HL (3) Bit manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand First Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY MOV1 $addr16 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
(4) Call instruction/branch instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand First Operand Basic instruction Compound instruction BR AX !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR, BC, BNC BZ, BNZ BT, BF BTCLR DBNZ
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
Preliminary Data Sheet
35
PD780053, 780054, 780055, 780056, 780058
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage Symbol VDD AVDD AVREF0 AVREF1 AVSS Input voltage VI1 P00-P05, P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131, X1, X2, XT2, RESET VI2 Output voltage VO P10-P17 1 pin P01-P05, P30-P37, P56, P57, P60-P67, P120-P127 total P10-P17, P20-P27, P40-P47, P50-P55, P70-P72, P130, P131 total Output current, low IOL Note 1 pin Peak value rms value P50-P55 total Peak value rms value P56, P57, P60-P63 total Peak value rms value P10-P17, P20-P27, P40-P47, P70-P72, P130, P131 total P01-P05, P30-P37, P64-P67, P120-P127 total Operating ambient temperature Storage temperature TA Peak value rms value Peak value rms value 30 15 100 70 100 70 50 20 50 20 -40 to +85 mA mA mA mA mA mA mA mA mA mA C Analog input pin P60-P63 N-ch Open-drain -0.3 to +16 -0.3 to VDD + 0.3 AVSS - 0.3 to AVREF0 + 0.3 -10 -15 -15 Test Conditions Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +0.3 -0.3 to VDD + 0.3 V V V V mA mA mA Unit V V V V V
Analog input voltage VAN Output current, high IOH
Tstg
-65 to +150
C
Note
rms value should be calculated as follows: [rms value] = [Peak value] x duty Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
Caution
36
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
Main System Clock Oscillation Circuit Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Recommended Circuit X2 X1 IC
Resonator Ceramic resonator
Parameter
Oscillator frequency (fx)
Note 1
Test Conditions VDD = Oscillator voltage range After VDD reaches oscillator voltage range MIN.
MIN. 1.0
TYP.
MAX. 5.0
Unit MHz
C2
C1
Oscillation stabilization time
Note 2
4
ms
Crystal resonator
X2
X1 IC
Oscillator frequency (fx)
Note 1
1.0
5.0
MHz
C2
C1
Oscillation stabilization time
Note 2
VDD = 4.5 to 5.5 V
10 30 1.0 5.0
ms
External clock
X1 input
MHz
X2
X1
frequency (fx) X1 input
Note 1
85
500
ns
PD74HCU04
high/low level width (tXH , tXL)
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wirinin the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS1. * Do not ground wiring to a ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured in software.
Preliminary Data Sheet
37
PD780053, 780054, 780055, 780056, 780058
Subsystem Clock Oscillation Circuit Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit IC XT2 R2 C4 C3 XT1 Parameter Oscillator frequency (fXT) Note 1 Oscillation stabilization time Note 2 XT1 input frequency (fXT) Note 1 XT1 input high/low level width (tXTH , tXTL) VDD = 4.5 to 5.5 V Test Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz
1.2
2 10
s
External clock
32
100
kHz
XT2
XT1
5
15
s
PD74HCU04
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN. Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines. * Wiring should not be placed close to a varying high current. * The potential of the oscillator capacitor ground should be the same as VSS1. * Do not ground wiring to a ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. 2. The subsystem clock oscillation circuit is a circuit with a low amplification level, more prone to misoperation due to noise than the main system clock. Therefore, when using the subsystem clock, take care with the wiring. Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance Input/output capacitance Symbol CIN Test Conditions f = 1 MHz Measured pins returned to 0 V. f = 1 MHz Measured pins returned to 0 V. P01-P05, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131 P60-P63 MIN. TYP. MAX. 15 Unit pF
CIO
15
pF
20
pF
Remark
The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified.
38
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter Input voltage, high Symbol VIH1 Test Conditions P10-P17, P21, P23, P30-P32, P35-P37, P40-P47, P50-P57, P64-P67, P71, P120-P127, P130, P131 P00-P05, P20, P22, P24-P27, P33, P34, P70, P72, RESET VIH3 P60-P63 (N-ch open-drain) VIH4 X1, X2 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V MIN. 0.7 VDD 0.8 VDD VDD = 2.7 to 5.5 V 0.8 VDD 0.85 VDD 0.7 VDD 0.8 VDD VDD-0.5 VDD-0.2 VIH5 XT1/P07, XT2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Note Input voltage, low VIL1 P10-P17, P21, P23, P30-P32, P35-P37, P40-P47, P50-P57, P64-P67, P71, P120-P127, P130, P131 P00-P05, P20, P22, P24-P27, P33, P34, P70, P72, RESET VIL3 P60-P63 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V VDD = 2.7 to 5.5 V 0.8 VDD 0.9 VDD 0.9 VDD 0 0 VDD = 2.7 to 5.5 V 0 0 0 0 0 VIL4 X1, X2 VDD = 2.7 to 5.5 V 0 0 VIL5 XT1/P07, XT2 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V Note Output voltage, high Output voltage, low VOL1 VOH VDD = 4.5 to 5.5 V, IOH = -1 mA IOH = -100 A P50-P57, P60-P63 P01-P05, P10-P17, P20-P27, P30-P37, P40-P47, P64-P67, P70-P72, P120-P127, P130, P131 VOL2 SB0, SB1, SCK0 VDD = 4.5 to 5.5 V, IOL = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA 0 0 0 VDD-1.0 VDD-0.5 0.4 2.0 0.4 TYP. MAX. VDD VDD VDD VDD 15 15 VDD VDD VDD VDD VDD 0.3 VDD 0.2 VDD 0.2 VDD 0.15 VDD 0.3 VDD 0.2 VDD 0.1 VDD 0.4 0.2 0.2 VDD 0.1 VDD 0.1 VDD Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V
VIH2
VIL2
VDD = 4.5 to 5.5 V, open-drain, pulled-up (R = 1 k)
0.2 VDD
V
VOL3
IOL = 400 A
0.5
V
Note Remark
For use as P07, use an inverter to input the reverse phase of P07 to the XT2 pin. The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Preliminary Data Sheet
39
PD780053, 780054, 780055, 780056, 780058
DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Test Conditions P00-P05, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P72, P120-P127, P130, P131, RESET X1, X2, XT1/P07, XT2 VIN = 15 V VIN = 0 V P60-P63 P00-P05, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131, RESET X1, X2, XT1/P07, XT2 P60-P63 VOUT = VDD VOUT = 0 V VIN = 0 V, P60-P63 VIN = 0 V, P01-P05, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P64-P67, P70-P72, P120-P127, P130, P131 20 15 40 30 MIN. TYP. MAX. 3 Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 80 -3
A A A
ILIL2 ILIL3 Output leakage current, high Output leakage current, low Mask option pull-up resistor Software pull-up resistor R2 ILOH ILOL R1
-20 -3 Note 3 -3 120 90
A A A A
k k
Note
For P60 to P63 without on-chip pull-up resistor (specifiable by mask option), a low-level input leakage current of -200 A (MAX.) flows only during the 1.5 clocks (no wait) after an instruction has been executed to read out port 6 (P6) or port mode register 6 (PM6). Outside the period of 1.5 clocks following executing a readout instruction, the current is -3 A (MAX.).
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
40
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter Power supply current Note 5 Symbol IDD1 Test Conditions 5.0 MHz Crystal oscillation operating mode (fXX = 2.5 MHz) Note 3 5.0 MHz Crystal oscillation operating mode (fXX = 5.0 MHz) Note 4 IDD2 5.0 MHz Crystal oscillation HALT mode (fXX = 2.5 MHz) Note 3 5.0 MHz Crystal oscillation HALT mode (fXX = 5.0 MHz) Note 4 IDD3 32.768 kHz Crystal oscillation operating mode Note 6 VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 2.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 2.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 2.0 V 10 % IDD4 32.768 kHz Crystal oscillation HALT mode Note 6 VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 2.0 V 10 % IDD5 XT1 = VDD STOP mode When feedback resistor is used XT1 = VDD STOP mode When feedback resistor is unused VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 2.0 V 10 % IDD6 VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 2.0 V 10 %
Note 1 Note 2 Note 2 Note 1 Note 2
MIN.
TYP. 4 0.6 0.35 6.5 0.8 1.4 0.5 280 1.6 0.65 60 32 24 25 5 2.5 1 0.5 0.3 0.1 0.05 0.05
MAX. 12 1.8 1.05 19.5 2.4 4.2 1.5 840 4.8 1.95 120 64 48 55 15 12.5 30 10 10 30 10 10
Unit mA mA mA mA mA mA mA
A
mA mA
A A A A A A A A A A A A
Notes 1. Operating in high-speed mode (when set the processor clock control register (PCC) to 00H). 2. Operating in low-speed mode (when set the PCC to 04H). 3. Operation with fXX = fX/2 (when oscillation mode selection register (OSMS) is set to 00H) 4. Operation with fXX = fX (when OSMS is set to 01H) 5. This current flows in the VDD and AVDD pins. However, a current flowing in the A/D converter, D/A converter, and on-chip pull-up resistor are not included. 6. When the main system clock is halted
Preliminary Data Sheet
41
PD780053, 780054, 780055, 780056, 780058
AC Characteristics (1) Basic operation (TA = -40 to +85 C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (Min. instruction execution time) Symbol TCY Test Conditions Operating on main system clock (fXX = 2.5 MHz)Note 1 Operating on main system clock (fXX = 5.0 MHz)Note 2 VDD = 3.5 to 5.5 V VDD = 2.7 to 3.5 V VDD = 2.7 to 5.5 V MIN. 0.8 2.0 0.4 0.8 40Note 3 2/fsam+0.1Note 4 2/fsam+0.2Note 4 2/fsam+0.5Note 4 TI01 input high/ low-level width TI1, TI2, TI5, TI6 input frequency TI1, TI2, TI5, TI6 input high/ low-level width Interrupt request input high/ low-level width INTP1-INTP5, P40-P47 VDD = 2.7 to 5.5 V tINTH tINTL INTP0 3.5 V VDD 5.5 V 2/fsam+0.1Note 4 2.7 V VDD < 3.5 V 2/fsam+0.2Note 4 2/fsam+0.5Note 4 10 20 RESET low level width tRSL VDD = 2.7 to 5.5 V 10 20 tTIH1 tTIL1 VDD = 4.5 to 5.5 V tTIH01 tTIL01 fTI1 VDD = 4.5 to 5.5 V VDD = 2.7 to 5.5 V 10 20 0 0 100 1.8 4 275 122 TYP. MAX. 64 64 32 32 125 Unit
s s s s s s s s s s
MHz kHz ns
Operating on subsystem clock TI00 input high/ low-level width tTIH00 tTIL00 3.5 V VDD 5.5 V 2.7 V VDD < 3.5 V
s s s s s s s s
Notes 1. Operation with fXX = fX/2 (when oscillation mode selection register (OSMS) is set to 00H) 2. Operation with fXX = fX (when OSMS is set to 01H) 3. Value when external clock is used. When a crystal resonator is used, it is 114 s (MIN.) 4. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is possible between fXX/2N, fXX/32, fXX/64 and fXX/128 (when N= 0 to 4).
42
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
TCY vs VDD (At fXX = fX/2 main system clock operation) TCY vs VDD (At fXX = fX main system clock operation)
60
60
Cycle Time TCY [s]
Cycle Time TCY [s]
10 Operation Guaranteed Range
10 Operation Guaranteed Range 2.0 1.0 0.5 0.4
2.0 1.0 0.5 0.4
0 1 2 3 4 5 6 Supply Voltage VDD [V]
0 1 2 3 4 5 6 Supply Voltage VDD [V]
Preliminary Data Sheet
43
PD780053, 780054, 780055, 780056, 780058
(2) Read/write operation (a) When MCS = 1, PCC2 to PCC0 = 000B (TA = -40 to +85 C, VDD = 4.5 to 5.5 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from RD in external fetch Address hold time from RD in external fetch Write data output time from RD Write data output time from WR Address hold time from WR RD delay time from WAIT WR delay time from WAIT tRDWD tWRWD tWRADH tWTRD tWTWR 40 0 0.85tCY 1.15tCY + 40 1.15tCY + 30 50 1.15tCY + 40 3.15tCY + 40 3.15tCY + 30 ns ns ns ns ns tWRWT tWTL tWDS tWDH tWRL tASTRD tASTWR tRDAST (1.15 + 2n)tCY (2.85 + 2n)tCY - 100 20 (2.85 + 2n)tCY - 60 25 0.85tCY + 20 0.85tCY - 10 1.15tCY + 20 0 (2 + 2n)tCY - 60 (2.85 + 2n)tCY - 60 0.85tCY - 50 2tCY - 60 2tCY - 60 (2 + 2n)tCY Test Conditions MIN. 0.85tCY - 50 0.85tCY - 50 50 (2.85 + 2n)tCY - 80 (4 + 2n)tCY - 100 (2 + 2n)tCY - 100 (2.85 + 2n)tCY - 100 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRDADH
0.85tCY - 50
1.15tCY + 50
ns
Remarks
1. 2. 3. 4.
MCS: Oscillation mode selection register (OSMS) bit 0 PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0 tCY = TCY/4 n indicates number of waits.
44
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
(b) When except MCS = 1, PCC2 to PCC0 = 000B (TA = -40 to +85 C, VDD = 2.0 to 5.5 V)
Parameter ASTB high-level width Symbol tASTH Test Conditions VDD = 2.7 to 5.5 V MIN. tCY - 80 tCY - 150 Address setup time tADS VDD = 2.7 to 5.5 V tCY - 80 tCY - 150 Address hold time tADH VDD = 2.7 to 5.5 V 0.4tCY - 10 0.37tCY - 40 Data input time from address tADD1 VDD = 2.7 to 5.5 V (3 + 2n)tCY - 160 (3 + 2n)tCY - 320 tADD2 VDD = 2.7 to 5.5 V (4 + 2n)tCY - 200 (4 + 2n)tCY - 300 Data input time from RD tRDD1 VDD = 2.7 to 5.5 V (1.4 + 2n)tCY - 70 (1.37 + 2n)tCY - 120 tRDD2 VDD = 2.7 to 5.5 V (2.4 + 2n)tCY - 70 (2.37 + 2n)tCY - 120 Read data hold time RD low-level width tRDH tRDL1 VDD = 2.7 to 5.5 V 0 (1.4 + 2n)tCY - 20 (1.37 + 2n)tCY - 20 tRDL2 VDD = 2.7 to 5.5 V (2.4 + 2n)tCY - 20 (2.37 + 2n)tCY - 20 WAIT input time from RD tRDWT1 VDD = 2.7 to 5.5 V tCY - 100 tCY - 200 tRDWT2 VDD = 2.7 to 5.5 V 2tCY - 100 2tCY - 200 WAIT input time from WR tWRWT VDD = 2.7 to 5.5 V 2tCY - 100 2tCY - 200 WAIT low-level width Write data setup time tWTL tWDS VDD = 2.7 to 5.5 V (1 + 2n)tCY (2.4 + 2n)tCY - 60 (2.37 + 2n)tCY - 100 Write data hold time WR low-level width tWDH tWRL VDD = 2.7 to 5.5 V 20 (2.4 + 2n)tCY - 20 (2.37 + 2n)tCY - 20 RD delay time from ASTB tASTRD VDD = 2.7 to 5.5 V 0.4tCY - 30 0.37tCY - 50 WR delay time from ASTB tASTWR VDD = 2.7 to 5.5 V 1.4tCY - 30 1.37tCY - 50 (2 + 2n)tCY MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
1. 2. 3. 4.
MCS: Oscillation mode selection register (OSMS) bit 0 PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0 tCY = TCY/4 n indicates number of waits.
Preliminary Data Sheet
45
PD780053, 780054, 780055, 780056, 780058
(b) When except MCS = 1, PCC2 to PCC0 = 000B (TA = -40 to +85 C, VDD = 2.0 to 5.5 V)
Parameter ASTB delay time from RD in external fetch Address hold time from RD in external fetch Write data output time from RD tRDWD VDD = 2.7 to 5.5 V 0.4tCY - 20 0.37tCY - 40 Write data output time from WR tWRWD VDD = 2.7 to 5.5 V 0 0 Address hold time from WR tWRADH VDD = 2.7 to 5.5 V tCY tCY RD delay time from WAIT tWTRD VDD = 2.7 to 5.5 V 0.6tCY + 180 0.63tCY + 350 WR delay time from WAIT tWTWR VDD = 2.7 to 5.5 V 0.6tCY + 120 0.63tCY + 240 60 120 tCY + 60 tCY + 120 2.6tCY + 180 2.63tCY + 350 2.6tCY+ 120 2.63tCY+ 240 ns ns ns ns ns ns ns ns ns ns Symbol tRDAST tRDADH Test Conditions MIN. tCY - 10 tCY - 50 MAX. tCY + 20 tCY + 50 Unit ns ns
Remarks
1. 2. 3. 4.
MCS: Oscillation mode selection register (OSMS) bit 0 PCC2 to PCC0: Processor clock control register (PCC) bit 2 to bit 0 tCY = TCY/4 n indicates number of waits.
46
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
(3) Serial interface (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK0 high/low-level width SI0 setup time (to SCK0) tSIK1 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V SI0 hold time (from SCK0) SO0 output delay time from SCK0 tKH1, tKL1 VDD = 4.5 to 5.5 V tKCY1/2 - 50 tKCY1/2 - 100 100 150 300 400
tKSI1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
400 C = 100 pF Note 300
tKSO1
ns
Note C is the load capacitance of SO0 output line. (ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter SCK0 cycle time Symbol tKCY2 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 2.0 V VDD 5.5 V MIN. 800 1600 3200 4800 SCK0 high/low-level width tKH2, tKL2 400 800 1600 2400 SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 SCK0 rise, fall time tR2, tF2 When using external device expansion function When not using external device expansion function 1000 ns tKSI2 C = 100 pF Note VDD = 2.0 to 5.5V tSIK2 100 150 400 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
tKSO2
300 500 160
ns ns ns
Note C is the load capacitance of SO0 output line.
Preliminary Data Sheet
47
PD780053, 780054, 780055, 780056, 780058
(iii) SBI mode (SCK0... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V SB0, SB1 setup time (to SCK0) tSIK3 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V MIN. 800 3200 4800 SCK0 high/low-level width tKH3, tKL3 tKCY3/2 - 50 tKCY3/2 - 150 100 300 400 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 tKSO3 R = 1 k , C = 100 pF tKSB tSBK
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns
tKSI3 VDD = 4.5 to 5.5 V
tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000
ns ns ns ns ns ns
SB0, SB1 high-level width tSBH SB0, SB1 low-level width tSBL
Note R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line. (iv) SBI mode (SCK0... External clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V 4.5 V VDD 5.5 V 2.0 V VDD < 4.5 V MIN. 800 3200 4800 SCK0 high/low-level width tKH4, tKL4 400 1600 2400 SB0, SB1 setup time (to SCK0) tSIK4 100 300 400 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tKSI4 tKSO4 R = 1 k , C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns
tKCY4/2 VDD = 4.5 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 When using external device expansion function When not using external device expansion function 1000 160 300 1000
ns ns ns ns ns ns ns ns
SB0, SB1 from SCK0 tKSB SCK0 from SB0, SB1 tSBK SB0, SB1 high-level width tSBH SB0, SB1 low-level width SCK0 rise, fall time tSBL tR4, tF4
Note R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
48
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
(v) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter SCK0 cycle time Symbol tKCY5 Test Conditions R = 1 k, C = 100 pF
Note
MIN. 1600 3200 4800
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
2.7 V VDD 5.5 V
SCK0 high-level width
tKH5
VDD = 2.7 to 5.5 V
tKCY5/2 - 160 tKCY5/2 - 190
SCK0 low-level width
tKL5
VDD = 4.5 to 5.5 V
tKCY5/2 - 50 tKCY5/2 - 100
SB0, SB1 setup time (to SCK0)
tSIK5
4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V
300 350 400 500
SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0
tKSI5
600
tKSO5
0
300
ns
Note R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line. (vi) 2-wire serial I/O mode (SCK0... Internal clock input)
Parameter SCK0 cycle time Symbol tKCY6 Test Conditions 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V MIN. 1600 3200 4800 SCK0 high-level width tKH6 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 650 1300 2100 SCK0 low-level width tKL6 2.7 V VDD 5.5 V 2.0 V VDD < 2.7 V 800 1600 2400 SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tKSI6 4.5 V VDD 5.5 V
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
tSIK6
VDD = 2.0 to 5.5 V
100 150 tKCY6/2
tKSO6
R = 1 k, C = 100 pF
0 0 0
300 500 800 160
ns ns ns ns
2.0 V VDD < 4.5 V
SCK0 rise, fall time
tR6, tF6
When using external device expansion function When not using external device expansion function
1000
ns
Note
R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
Preliminary Data Sheet
49
PD780053, 780054, 780055, 780056, 780058
(b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1...Internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK1 high/low-level width tKH7, tKL7 VDD = 4.5 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V tKCY7/2-50 tKCY7/2-100 SI1 setup time (to SCK1) tSIK7 100 150 300 400 SI1 hold time (from SCK1) SO1 output delay time from SCK1 tKSI7 tKSO7 C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
400 300
ns
Note C is the load capacitance of the SO1 output line. (ii) 3-wire serial I/O mode (SCK1...External clock input)
Parameter SCK1 cycle time Symbol tKCY8 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK1 high/low-level width tKH8, tKL8 400 800 1600 2400 SI1 setup time (to SCK1) tSIK8 VDD = 2.0 to 5.5 V 100 150 SI1 hold time (from SCK1) SO1 output delay time from SCK1 tKIS8 tKSO8 C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
400 VDD = 2.0 to 5.5 V 300 500
ns ns ns ns
SCK1 rise, fall time
tR8, tF8
When using external device expansion function When not using external device expansion function
160 1000
Note
C is the load capacitance of the SO1 output line.
50
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...Internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK1 high/low-level width tKH9, tKL9 VDD = 4.5 to 5.5 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V tKCY9/2-50 tKCY9/2-100 SI1 setup time (to SCK1) tSIK9 100 150 300 400 SI1 hold time (from SCK1) SO1 output delay time from SCK1 STB from SCK1 Strobe signal high-level width tKSI9 tKSO9 tSBD tSBW 2.7 V VDD < 5.5 V 2.0 V < VDD < 2.7 V C = 100 pF Note tKCY9/2-100 tKCY9-30 tKCY9-60 tKCY9-90 Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) tBYH 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 100 150 200 300 SCK1 from busy inactive tSPS 2tKCY9 ns ns ns ns ns tBYS 100 400 300 tKCY9/2+100 tKCY9+30 tKCY9+60 tKCY9+90 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note
C is the load capacitance of the SO1 output line.
Preliminary Data Sheet
51
PD780053, 780054, 780055, 780056, 780058
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...External clock input)
Parameter SCK1 cycle time Symbol tKCY10 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V tKH10, tKL10 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK1 high/low-level width 400 800 1600 2400 SI1 setup time (to SCK1) tSIK10 VDD = 2.0 to 5.5 V 100 150 SI1 hold time (from SCK1) SO1 output delay time from SCK1 tKSI10 tKSO10 C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
400 VDD = 2.0 to 5.5 V 300 500
ns ns ns ns
SCK1 rise, fall time
tR10, tF10
When using external device expansion function When not using external device expansion function
160 1000
Note
C is the load capacitance of the SO1 output line.
52
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
(c) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2...Internal clock output)
Parameter SCK2 cycle time Symbol tKCY11 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 SCK2 high/low-level width tKH11, tKL11 VDD = 4.5 to 5.5 V tKCY11/2-50 tKCY11/2-100 SI2 setup time (to SCK2) tSIK11 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 100 150 300 400 SI2 hold time (from SCK2) SO2 output delay time from SCK2 tKSI11 tKSO11 C = 100 pF Note 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns
Note
C is the load capacitance of the SO2 output line. (ii) 3-wire serial I/O mode (SCK2...External clock input)
Parameter Symbol tKCY12 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns 300 500 ns ns ns
SCK2 cycle time
SCK2 high/low-level width
tKH12, tKL12
400 800 1600 2400
SI2 setup time (to SCK2)
tSIK12
VDD = 2.0 to 5.5 V
100 150
SI2 hold time (from SCK2) SO2 output delay time from SCK2
tKSI12 tKSO12 C = 100 pF
Note
400 VDD = 2.0 to 5.5 V
SCK2 rise, fall time
tR12,
Other than below VDD = 4.5 to 5.5 V When not using external device expansion function
160 1
tF12
s
Note
C is the load capacitance of the SO2 output line.
Preliminary Data Sheet
53
PD780053, 780054, 780055, 780056, 780058
(iii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. TYP. MAX. 78125 39063 19531 9766 Unit bps bps bps bps
(iv) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY13 Test Conditions 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V tKH13, tKL13 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V 4.5 V VDD 5.5 V 2.7 V VDD < 4.5 V 2.0 V VDD < 2.7 V MIN. 800 1600 3200 4800 ASCK high-/low-level width 400 800 1600 2400 Transfer rate 39063 19531 9766 6510 ASCK rise, fall time tR13, tF13 VDD = 4.5 to 5.5 V, when not using external device expansion function. 160 ns 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns bps bps bps bps ns
54
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timing
1/fX
tXL
tXH VIH4 (MIN.) VIL4 (MAX.)
X1 Input
1/fXT
tXTL XT1 Input
tXTH VIH5 (MIN.) VIL5 (MAX.)
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1 tTIL1 tTIH1
TI1,TI2
Preliminary Data Sheet
55
PD780053, 780054, 780055, 780056, 780058
Read/Write Operation External fetch (no wait) :
A8-A15
High-Order 8-Bit Address tADD1
AD0-AD7 tADS tASTH ASTB
Low-Order 8-Bit Address
Hi-Z
Operation Code tRDD1 tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
External fetch (wait insertion) :
A8-A15
High-Order 8-Bit Address
tADD1 AD0-AD7 tADS tASTH ASTB
Low-Order 8-Bit Address
Hi-Z tRDD1
Operation Code tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
56
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
External data access (no wait) :
A8-A15
High-Order 8-Bit Address
tADD2 AD0-AD7 tADS tADH tASTH ASTB
Low-Order 8-Bit Address
Hi-Z tRDD2
Read Data
Hi-Z
Write Data
Hi-Z
tRDH
RD tASTRD tRDL2 tRDWD tWRWD WR tASTWR tWRL tWDS tWDH tWRADH
External data access (wait insertion) :
A8-A15
High-Order 8-Bit Address
tADD2 AD0-AD7 tADS tADH tASTH ASTB
Low-Order 8-Bit Address
Hi-Z tRDD2
Read Data
Hi-Z
Write Data
Hi-Z
tRDH
tASTRD RD tRDL2 tRDWD tWDWR WR tASTWR tWRL tWRADH tWDS tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
Preliminary Data Sheet
57
PD780053, 780054, 780055, 780056, 780058
Serial Transfer Timing 3-wire serial I/O mode :
tKCYm tKLm tRn SCK0-SCK2 tSIKm tKSIm tKHm tFn
SI0-SI2 tKSOm
Input Data
SO0-SO2
Output Data
m = 1, 2, 7, 8, 11, 12 n = 2, 8, 12
SBI mode (bus release signal transfer) :
tKCY3, 4 tKL3, 4 tR4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 tF4
SB0, SB1 tKSO3, 4
SBI mode (command signal transfer) :
tKCY3,4
tKL3, 4 tR4 SCK0
tKH3, 4
tF4
tSIK3, 4 tKSB tSBK tKSI3, 4
SB0, SB1 tKSO3, 4
58
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
2-wire serial I/O mode :
tKCY5, 6
tKL5, 6 tR6 SCK0 tSIK5, 6 tKSO5, 6 SB0, SB1
tKH5, 6 tF6
tKSI5, 6
3-wire serial I/O mode with automatic transmit/receive function :
SO1
D2
D1
D0
D7
SI1
D2 tSIK9, 10
D1 tKSI9, 10 tKH9, 10
D0
D7
tKSO9, 10
tF10
SCK1
tR10
tKL9, 10
tSBD
tSBW
STB
tKCY9, 10
3-wire serial I/O mode with automatic transmit/receive function (busy processing) :
SCK1
7
8
9 Note
10 Note tBYS
10+n Note tBYH tSPS
1
BUSY (Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
Preliminary Data Sheet
59
PD780053, 780054, 780055, 780056, 780058
UART mode (external clock input) :
tKCY13 t KL13 tR13 tKH13 tF13
ASCK
A/D Converter Characteristics (TA = -40 to +85 C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall errorNote tCONV tSAMP VIAN AVREF0 IREF0 When A/D converter is operatingNote 2 When A/D converter is not operatingNote 3 Resistance between AVREF0 and AVSS RREF0 When A/D conversion is not performed 4 16 12/fxx AVSS 2.7 500 0 14 AVREF0 AVDD 1500 3 Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 1.0 100 Unit bit %
Conversion time Sampling time Analog input voltage Reference voltage AVREF0 current
s s
V V
A A
k
Notes 1. Overroll error excluding quantization error (1/2 LSB). It is indicated as a ratio to the full-scale value. 2. The current flowing to AVREF0 pin when bit 7 (CS) of the A/D converter mode register (ADM) is 1. 3. The current flowing to AVREF0 pin when bit 7 (CS) of the A/D converter mode regidter (ADM) is 0. Remark fxx : Main system clock frequency (fX or fX/2) fx : Main system clock oscillation frequency D/A Converter Characteristics (TA = -40 to +85 C, VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter Resolution Overall error R = 2 MNote 1 R=4 MNote 1 MNote 1
Note 1
Symbol
Test Conditions
MIN.
TYP.
MAX. 8 1.2 0.8 0.6 10 15
Unit bit % % %
R = 10 Settling time
AVREF1 = 4.5 to 5.5 V
C=30pF Output resistance Analog reference voltage AVREF1 current RO AVREF1 IREF1 Note 2 Note 2
s s
k
8 2.7 VDD 2.5 4 8
V mA k
Resistance between AVREF1 and AVSS RAIREF1
DACS0, DACS1 = 55HNote 2
Notes 1. R and C denote D/A converter output pin load resistance and load capacitance, respectively. 2. Value for 1 D/A converter channel Remark DACS0 and DACS1: D/A conversion value setting register 0 and 1
60
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention power supply voltage Data retention power supply current Symbol VDDDR Test Conditions MIN. 1.8 TYP. MAX. 5.5 Unit V
IDDDR
VDDDR = 1.8 V Subsystem clock stop and feed-back resistor disconnected 0 Release by RESET Release by interrupt
0.1
10
A
Release signal set time Oscillation stabiliation wait time
tSREL tWAIT
s
2 /fx Note
17
ms ms
Note
In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS) , selection of 212/fXX and 214/fXX to 217/fXX is possible. fXX: Main system clock frequency (fX or fX/2) fX : Main system clock oscillatior frequency
Remark
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retension Mode
VDD STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Operating Mode
Data Retension Mode
VDD STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
Preliminary Data Sheet
61
PD780053, 780054, 780055, 780056, 780058
Interrupt Input Timing
tINTL INTP0-INTP5
tINTH
RESET Input Timing
tRSL
RESET
62
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
12. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x14)
A B
60 61
41 40
detail of lead end
C
D
S R Q
80 1
21 20
F G P H I
M
J K M
N
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. INCHES 0.6770.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.0550.004 0.0050.003 3 +7 -3 0.067 MAX. P80GC-65-8BT
Preliminary Data Sheet
63
PD780053, 780054, 780055, 780056, 780058
80 PIN PLASTIC TQFP (FINE PITCH) (
A B
12)
60 61
41 40
detail of lead end
C
D
S Q
80
21 1 20
F
G
H
I
M
J
K
P
N L
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145 +0.055 -0.045 0.10 1.05 0.050.05 55 1.27 MAX. INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.041 0.0020.002 55 0.050 MAX. P80GK-50-BE9-4
64
Preliminary Data Sheet
M
R
PD780053, 780054, 780055, 780056, 780058
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for developing systems using the PD780058 subseries. Refer to (5) Cautions when the development tools are used. (1) Language processing software
RA78K/0 CC78K/0 DF780058 CC78K/0-L 78K/0 series common assembler package 78K/0 series common C compiler package Device file for the PD780058 subseries 78K/0 series common C compiler library source file
(2) Flash memory writing tools
Flashpro II (Part number: FL-PR2) FA-80GC Note FA-80GK Note Dedicated flash programmer for microcomputers incorporating flash memory Adapter for flash memory writing
Note Under development (3) Debugging tools * When using the IE-78K0-NS in-circuit emulator
IE-78K0-NS Note IE-70000-MC-PS-B IE-70000-98-IF-C Note IE-70000-CD-IF Note IE-70000-PC-IF-C Note IE-780308-NS-EM1 Note NP-80GC Note NP-80GK Note TGK-080SDW EV-9200GC-80 ID78K0-NS Note SM78K0 DF780058 78K/0 series common in-circuit emulator Power supply unit for IE-78K0-NS Interface adapter necessary when a PC-9800 series computer (except notebook-type personal computer) is used as host machine PC card and interface cable necessary when a PC-9800 series notebook-type personal computer is used as host machine Interface adapter necessary when an IBM PC/AT TM or a compatible machine is used as host machine Emulation board common to the PD780308 subseries Emulation probe for 80-pin plastic QFP (GC-8BT type) Emulation probe for 80-pin plastic TQFP (GK-BE9 type) Conversion adapter to connect the board of the target system to be mounted on 80-pin plastic TQFP (GK-BE9 type) and NP-80GK Socket to be mounted on the board of the target system for 80-pin plastic QFP (GC-8BT type) Integrated debugger for IE-78K0-NS 78K/0 series common system simulator Device file for the PD780058 subseries
Note Under development
Preliminary Data Sheet
65
PD780053, 780054, 780055, 780056, 780058
* When using the IE-78001-R-A in-circuit emulator
IE-78001-R-A Note IE-70000-98-IF-B IE-70000-98-IF-C Note IE-70000-PC-IF-B IE-70000-PC-IF-C Note IE-78000-R-SV3 IE-780308-NS-EM1 IE-780308-R-EM IE-78K0-R-EX1 Note EP-78230GC-R EP-78054GK-R TGK-080SDW EV-9200GC-80 ID78K0 SM78K0 DF780058
Note
78K/0 series common in-circuit emulator Interface adapter necessary when a PC-9800 series computer (except notebook-type personal computer) is used as host machine Interface adapter necessary when an IBM PC/AT or a compatible machine is used as host machine Interface adapter and cable necessary when an EWS is used as host machine Emulation board common to the PD780308 subseries Emulation probe conversion board necessary when the IE-780308-NS-EM1 is used in the IE-78001-R-A. Emulation probe for 80-pin plastic QFP (GC-8BT type) Emulaiton probe for 80-pin plastic TQFP (GK-BE9 type) Conversion adapter to connect the board of the target system to be mounted on 80-pin plastic TQFP (GK-BE9 type) and EP-78054GK-R Socket to be mounted on the board of the target system made for the 80-pin plastic QFP (GC-8BT type) Integrated debugger for IE-78001-R-A 78K/0 series common system simulator Device file for the PD780058 subseries
Note Under development (4) Real-time OS
RX78K/0 MX78K0 Real-time OS for 78K/0 series OS for 78K/0 series
66
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
(5) Cautions when the development tools are used * The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780058. * The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and DF780058. * Flashpro II, FA-80GC, FA-80GK, NP-80GC, and NP-80GK are products of Naito Densei Machida Mfg. Co., Ltd. (TEL: (044)822-3813). Contact an NEC distributor when purchasing these products. * TGK-080SDW is a product of Tokyo Eletech Corp. Inquiry : Daimaru Kogyo, Ltd. Electronics Dept. (TEL: Tokyo (03) 3820-7112) Electronics 2nd Dept. (TEL: Osaka (06) 244-6672) * Refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development tools. * Host machines and OSs compatible with the software are as follows:
Host Machine [OS] PC PC-9800 Series IBM PC/AT and compatible machines [Japanese/English Windows]
Note Note
EWS HP9000 series 700 TM [HP-UX TM ] SPARCstation TM [SunOS TM] NEWS TM (RISC) [NEWS-OS TM ]
[Windows TM ]
Software RA78K/0 CC78K/0 ID78K0-NS ID78K0 SM78K0 RX78K/0 MX78K0
-
-
Note Note
Note DOS based software
Preliminary Data Sheet
67
PD780053, 780054, 780055, 780056, 780058
APPENDIX B. RELATED DOCUMENTS
Documents Related Devices
Document No. Document Name Japanese English U12013E This document U12092E U12326E -- --
PD780058, 780058Y Subseries User's Manual PD780053, 780054, 780055, 780056, 780058 Data Sheet PD78F0058 Preliminary Product Information
78K/0 Series User's Manual - Instruction 78K/0 Series Instruction Table 78K/0 Series Instruction Set
U12013J U12182J U12092J U12326J U10903J U10904J
Development Tool Documents (User's Manual)
Document No. Document Name Japanese RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler Operation Language CC78K/0 C Compiler Application Note CC78K Series Library Source File IE-78K0-NS IE-78001-R-EM IE-780308-NS-EM1 IE-780308-R-EM EP-78230 EP-78054GK-R SM78K0 System Simulator Windows Based Reference External Part User Open Interface Specifications PC Based Reference Reference Reference Guide Programming Know-How U11802J U11801J U11789J U12323J U11517J U11518J U13034J U12322J Planned Planned Planned U11362J EEU-985 EEU-932 U10181J U10092J U12900J U11151J U11539J U11649J English U11802E U11801E U11789E EEU-1402 U11517E U11518E U13034E -- Planned Planned Planned U11362E EEU-1515 EEU-1468 U10181E U10092E Planned -- U11539E U11649E
SM78K Series System Simulator ID78K0-NS Integrated Debugger ID78K0 Integrated Debugger ID78K0 Integrated Debugger ID78K0 Integrated Debugger
EWS Based PC Based Windows Based
Caution
The documents listed above are subject to change without notice. Be sure to use the latest documents for designing your system.
68
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
Documents Related to Embedded Software (User's Manual)
Document No. Document Name Japanese 78K/0 Series Real-Time OS Fundamentals Installation 78K/0 Series OS MX78K0 Fundamental U11537J U11536J U12257J English U11537E U11536E U12257E
Other Related Documents
Document No. Document Name Japanese IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Device Quality/Reliability Handbook Microcomputer Product Series Guide C10943X C10535J C11531J C10983J C11892J C12769J U11416J C10535E C11531E C10983E C11892E -- -- English
Caution
The documents listed above are subject to change without notice. Be sure to use the latest documents for designing your system.
Preliminary Data Sheet
69
PD780053, 780054, 780055, 780056, 780058
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
70
Preliminary Data Sheet
PD780053, 780054, 780055, 780056, 780058
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J98. 11
Preliminary Data Sheet
71
PD780053, 780054, 780055, 780056, 780058
FIP and IEbus are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

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